Welcome to Imran Ahmed's Data Connection (IADC)! I completed my PhD in the Department of Electrical and Computer Engineering at the University of Toronto, under the supervision of Professor David A. Johns. I was with the Electronics Group working on mixed signal research. I co-founded Kapik Integration, a Toronto area start-up whose expertise is enabling next generation technologies with 'smart analog' approaches.

My Masters and Doctorial research was focused on various aspects of pipeline ADCs. For my Master's work I developed a 10-bit power scaleable ADC which was able to have its power scale from 1kS/s (15uW) to 50MS/s (35mW). My PhD research was aimed at developing advanced calibration schemes for pipeline ADCs, developing circuit techniques to reduce ADC power for sub-sampling applications, and developing very low power pipelined ADC architectures. At Kapik I have been involved on a variety of different mixed-signal circuits from low speed sensor interfaces to high speed data communication.

I am also author of a book 'Pipelined ADC Design and Enhancement Techniques' (Springer 2010). The book provides a general overview of pipelined ADC design as well as a detailed discussion of several state-of-the-art implementations.

You can reach me by e-mail at: imran (dot) ahmed (at) utoronto (dot) ca

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"A 3-axis PZT based MEMS Gyroscope in 0.18um CMOS"
ESSCIRC 2012, Bordeaux, France
[paper] [slides]

'A low-power capacitive charge pump  based pipelined ADC'

May 2010 JSSC [paper]

ISSCC 2009

February '09, San Francisco, USA

[paper] [slides]


Advances in Analog Circuit Design

Workshop: Smart Data Converters, March 31-April 2, '09, Lund, Sweden,


Co-founder, Director



Two papers in July 2008 JSSC

Young Scientist award for best student paper published at ESSCIRC 2007


2008 Analog Devices Outstanding Student Designer Award


2007 Internship, @ Broadcom Netherlands


"An 11-bit 45MS/s pipelined ADC with rapid calibration of DAC errors in a multi-bit pipeline stage"

 Sept. 2007, Munich, Germany

[paper] [slides]


"A high bandwidth power scaleable sub-sampling 10-bit pipelined ADC with embedded sample and hold"

 Sept. 2007, Munich, Germany

[paper] [slides]


1st place finish, and best overall submission in 2005 DAC/ISSCC student design competition


December 2005, JSSC paper


 ISSCC 2005, session 15.3