My PhD research was aimed at developing various pipelined ADC enhancement techniques. The areas of focus were: linearity enhancement and power reduction. The body of work consisted of three fabricated chips.

The first part of my PhD was based on developing techniques to rapidly estimate and correct errors in Pipelined Analog to Digital Converters (ADCs). Measured results from an 11-bit pipelined ADC in 1.8V 0.18um CMOS show that DAC errors in a multi-bit pipeline stage can be corrected in ~10,000 clock cycles. Details of this work were published at ESSCIRC 2007, and are available in the publications section of this website. This work received the 'Young Scientist Award' (best student paper) at ESSCIRC 2007.

The second part of my PhD looked at developing a 10-bit pipelined ADC which had an embedded Sample and Hold circuit for use in sub-sampled systems. Measured results from a 1.8V 0.18um CMOS chip showed the ADC to achieve more than 51dB of SNDR for input frequencies higher than 270MHz, although no front-end sample and hold was used. Details of this work were published at ESSCIRC 2007, and are available in the publications section of this website.

The third part of my PhD looked at developing low power pipelined ADCs, which was presented at ISSCC 2009. A capacitive charge-pump inspired technique was combined with source-followers to achieve stage gain in the pipelined ADC with low power, rather than using opamps with feedback. The 10b 50MS/s ADC in 1.8V 0.18Ám CMOS achieved a peak SNDR/SFDR of 58.2/66dB, while consuming 3.9mW for all active circuits and 6mW for all clocking circuits.

My Masters research was based on an ADC which has its power scaleable with sampling rate (fs), i.e. lower fs=> lower power consumption.   The key challenge in this work was being able to scale analog power (digital power already scales with sampling rate but is a small percentage of overall ADC power) over very large variations in sampling rate.

A novel opamp architecture with rapid power on times, and a power on/off architecture was used to develop an ADC architecture which had a wide power-sampling rate dependency which multiplies the power scaleable range of current scaling by >50x, thereby improves on previous publications which rely exclusively on current scaling.

A prototype was fabricated for the thesis in a 0.18um CMOS process through CMC and was found to be fully functional between fs=1kS/s (15uW) to 50MS/s (35mW). This work was published at ISSCC 2005, and in the December 2005 JSSC. More details of this work are available in the publications section. This work won first place and best overall submission in the 2005 DAC/ISSCC student design competition.

Fast DAC calibration chip in an 11-bit 45MS/s pipelined ADC

Embeded Sample and Hold ADC for sub-sampled systems

Low power pipelined ADC

Power scaleable 1kS/s (15uW) to 50MS/s (35mW) 10-bit ADC